1. Field of the Invention
The present invention relates generally to nonvolatile semiconductor memory devices and, more particularly, to nonvolatile semiconductor memory devices capable of increasing the number of times memory cells can reliably be rewritten and limiting cell current reduction in an extended storage time period memory device.
2. Description of the Related Art
In recent years nonvolatile semiconductor memory devices have become more important. Nonvolatile memories include ferro-electric random access memories (FRAM), erasable programmable read-only memories (EPROM), electrically erasable programmable read-only memories (EEPROM), and similar devices. EPROMs and EEPROMs store data by accumulating electrical charge carriers on the floating gate of a memory transistor. A control gate within the memory transistor is used to detect a variation in the threshold voltage of the memory due to the presence or absence of programming charge on the gate of the memory transistor. EEPROMs include "Flash" EEPROMs which provide an array of memory cells divided into sub-arrays or "blocks" where data erasure is performed in units of complete blocks.
Flash-EEPROMs include memory cells which may be generally categorized into two types: the split gate type and the stacked gate type. A conventional Flash-EEPROM cell of the split gate type is illustrated in PCT Publication No. WO92/18980. FIG. 1 illustrates, in cross-section, a single memory cell 101 of the split gate type as shown in the Publication. Referring now to FIG. 1, the illustrated p-type single-crystal silicon substrate 102 has n-type source S and drain D regions formed on its surface. The source S and drain D define therebetween a channel region CH, above which a floating gate FG is formed. The floating gate FG is separated from the channel region CH by a first dielectric film 103. A control gate CG is formed extending partially over the floating gate FG with a second dielectric film 104 separating the control gate CG from the floating gate FG. A portion of the control gate CG is disposed over the channel CH and is separated from the channel CH by the first dielectric film 103 so that control gate CG can be used as a select gate 105 for the memory transistor. Data storage is accomplished by accumulating electrons in the floating gate FG using in part a voltage applied to the control gate CG and interacting with the floating gate FG through the second dielectric film 104.
In those memory devices of the type shown in FIG. 1, which may store electrons in the floating gate FG, the cell current that flows through the memory cell decreases as the memory device is subjected to repeated data rewriting cycles. This reduced cell current may result in the memory cell being unable to reliably perform the data write and read operations required by normal operation of the memory cell. Presumably, the reduced cell current is caused by repeated rewrite operations physically damaging or degrading the quality of the second dielectric film 104. In turn, a damaged dielectric film 104 may make it difficult for electrons to "escape" from the floating gate FG and may trap once-escaped electrons within the second dielectric film 104. The trapped electrons may then return to the floating gate FG, whereby the potential applied to the floating gate FG is effectively reduced so that the channel is not well formed beneath the floating gate FG.
Another disadvantage observed when using conventional floating gate memories is that the time period over which data can be reliably stored is limited. In other words, with conventional floating gate memories there is a risk of data alteration after the elapse of a certain time period resulting in lack of reliability. Data can be altered as electrons leak through the dielectric film to a floating gate FG that is in the erase state, which results in this gate unintentionally changing to an electron injected state.